Circuit Diagrams
Complete circuit configuration shown in stages.
Power Flow Overview
This diagram shows the complete power conversion chain from USB-C input to all output rails, including the relationship between all circuit diagrams.
Power Conversion Strategy:
- Two-stage design: DC-DC converters provide efficient voltage reduction, linear regulators provide low-noise final outputs
- +12V rail: USB-C 15V → Buck (U2) → LDO (U6) → +12V OUT
- +5V rail: USB-C 15V → Buck (U3) → LDO (U7) → +5V OUT
- -12V rail: USB-C 15V → Inverting Buck-Boost (U4) → LDO (U8) → -12V OUT
Diagram1: USB-PD Power Supply Section (STUSB4500)
v1.1 Upgrade
This section documents the STUSB4500-based design (v1.1). The STUSB4500 is USB-IF certified with ~95%+ charger compatibility. For the deprecated CH224D design (v1.0), see CH224D documentation.
Diagram1-1: Complete STUSB4500 Circuit with Load Switch
VBUS_IN (from USB-C J1)
│
┌───────────────────────────────┼───────────────────────────────────┐
│ │ │
│ R11 (100kΩ) │
│ │ │
│ ├──────── Q1 (AO3401A) ─────────────┤
│ │ S ←───── D │
│ R12 (56kΩ) │ │
│ │ G │
│ │ │ │
│ STUSB4500 (QFN-24) │ │ │
│ ┌────────────────────┐ │ │ │
│ │ │ │ │ │
│ │ VBUS_EN_SNK ──────┼──────┘ │ │
│ │ (pin 16) │ │ │
│ │ │ C35 (100nF) │
│ │ VDD (pin 24) ─────┼── VBUS_IN │ │
│ │ │ │ GND │
│ │ C2 (100nF) │ │
│ │ │ │ ▼ │
│ │ GND │ VBUS_OUT ──→ (to DC-DC) │
│ │ │ │ │
│ │ VREG_2V7 (pin 23) │ TP1 │
│ │ │ │ │
│ │ C30 (1µF) │ │
│ │ │ │ │
│ │ GND │ │
│ │ │ │
│ │ VREG_1V2 (pin 21) │ │
│ │ │ │ │
│ │ C34 (1µF) │ │
│ │ │ │ │
│ │ GND │ │
│ │ │ │
│ │ VSYS (pin 22) ────┼── VREG_2V7 (tie together) │
│ │ │ │
│ │ RESET (pin 6) ────┼── GND (internal pull-down, NC also OK) │
│ │ │ │
│ │ DISCH (pin 9) ────┼── R13 (470Ω) ── VBUS_OUT │
│ │ │ │
│ │ ADDR0 (pin 12) ───┼── GND │
│ │ ADDR1 (pin 13) ───┼── GND │
│ │ │ │
│ │ GND (pin 10) │ │
│ │ EP (pin 25) ──────┼── GND │
│ │ │ │
│ │ CC1 (pin 2) ──────┼────┬── USB-C CC1 │
│ │ CC1DB (pin 1) ────┼────┘ │
│ │ │ │ │
│ │ CC2 (pin 4) ──────┼────┼─┬── USB-C CC2 │
│ │ CC2DB (pin 5) ────┼────┼─┘ │
│ │ │ │ │
│ └────────────────────┘ │ │
│ │ │
│ ESD Protection D4 (USBLC6-2SC6): │
│ ┌──────────────────────┐ │
│ │ Pin 1 (I/O1) ────────┼─ USB-C CC1 ─→ Pin 6 (I/O1) ─→ CC1 │
│ │ Pin 3 (I/O2) ────────┼─ USB-C CC2 ─→ Pin 4 (I/O2) ─→ CC2 │
│ │ Pin 2 (GND) ────────┼─ GND │
│ │ Pin 5 (VBUS) ────────┼─ VBUS_IN │
│ └──────────────────────┘ │
│ │
└───────────────────────────────────────────────────────────────────┘
│
GND
USB-C Connector J1 (6-pin power-only):
┌─────────────────────────────────────┐
│ A9,B9 VBUS ──────────────────────┼──→ VBUS_IN Rail (5V initially)
│ │
│ A5 CC1 ──────────────────────┼──→ To STUSB4500 CC1 (pin 2)
│ B5 CC2 ──────────────────────┼──→ To STUSB4500 CC2 (pin 4)
│ │
│ A1,B12 GND ──────────────────────┼──→ System GND
└─────────────────────────────────────┘
Diagram1-2: Load Switch Operation (Power Path Control)
Power Path with P-Channel MOSFET Load Switch:
VBUS_IN (15V after PD negotiation)
│
R11 (100kΩ) ← Gate pull-up (default OFF)
│
VBUS_EN_SNK ───┬── R12 (56kΩ) ──┴─── Gate ─── Q1 (AO3401A)
(from STUSB4500)│ │ │
│ Source Drain
C35 (100nF) │ │
│ VBUS_IN │
GND ▼
VBUS_OUT (to DC-DC)
Load Switch Operation:
┌────────────────────────────────────────────────────────────────────┐
│ State │ VBUS_EN_SNK │ Gate Voltage │ Q1 State │ Output│
├────────────────────┼─────────────┼──────────────┼──────────┼───────┤
│ No cable / PD fail │ LOW (0V) │ HIGH (VBUS) │ OFF │ 0V │
│ PD negotiation OK │ HIGH (~3V) │ LOW (~2V) │ ON │ 15V │
└────────────────────────────────────────────────────────────────────┘
Why P-Channel MOSFET?
- Simple high-side switch (no charge pump needed)
- Gate referenced to VBUS (easy to drive with VBUS_EN_SNK)
- Default OFF when gate is pulled to VBUS via R11
Soft-Start Calculation:
- Time constant: τ = R12 × C35 = 56kΩ × 100nF = 5.6ms
- Limits dV/dt during turn-on, reducing inrush current
Diagram1-3: USB PD Negotiation Process (STUSB4500)
Step-by-step PD negotiation sequence:
1. Initial Connection (0-100ms):
┌─────────┐ ┌───────────┐
│ USB-C │ ─── VBUS (5V) ───→ │ STUSB4500 │──→ Q1 OFF (no output)
│ PD │ │ │
│ Adapter │ ← CC1/CC2 pins ─→ │ (handles │
└─────────┘ │ Rd int.) │
└───────────┘
VBUS = 5V (default USB voltage)
STUSB4500 presents Rd internally (no external 5.1kΩ needed)
VBUS_EN_SNK = LOW → Q1 OFF → VBUS_OUT = 0V
2. Capability Discovery (100-200ms):
STUSB4500 requests Source Capabilities via CC
PD Adapter responds: 5V, 9V, 12V, 15V, 20V profiles
3. Voltage Request (200-300ms):
STUSB4500 requests 15V (from NVM configuration)
Built-in retry on failure (unlike CH224D)
4. Acceptance & Voltage Transition (300-500ms):
PD Adapter accepts request
VBUS transitions: 5V → 15V
STUSB4500 waits for stable VBUS
5. Power Ready (>500ms):
STUSB4500 confirms 15V stable
VBUS_EN_SNK goes HIGH → Q1 turns ON
VBUS_OUT = 15V (power delivered to DC-DC stages)
KEY DIFFERENCE from CH224D:
- Q1 prevents power delivery until PD negotiation succeeds
- No 5V exposure to downstream circuits
- Clean startup without voltage transitions on output
Diagram1-4: STUSB4500 Pin Configuration
STUSB4500 (QFN-24) - USB-IF Certified PD Sink Controller:
┌───────────────────────────────────────┐
│ (Top View) │
│ │
CC1DB 1 │● 24│ VDD ─── VBUS_IN + C2 (100nF)
CC1 2 │ 23│ VREG_2V7 ── C30 (1µF) ── GND
NC 3 │ 22│ VSYS ── VREG_2V7
CC2 4 │ 21│ VREG_1V2 ── C34 (1µF) ── GND
CC2DB 5 │ 20│ POWER_OK2 (NC)
RESET 6 │── GND (or NC) 19│ ALERT (NC)
SCL 7 │── NC (or I2C) 18│ VBUS_VS_DISCH (NC)
SDA 8 │── NC (or I2C) 17│ A_B_SIDE (NC)
DISCH 9 │── R13 (470Ω) ── VBUS_OUT 16│ VBUS_EN_SNK ──→ Gate drive
GND 10 │── GND 15│ GPIO (NC)
ATTACH 11 │── NC 14│ POWER_OK3 (NC)
ADDR0 12 │── GND 13│ ADDR1 ── GND
│ │
│ ┌──────────────┐ │
└─────────┤ EP (pin 25) ├──────────────┘
│ GND │
└──────────────┘
Critical Pin Connections:
┌──────────────┬──────────────────────────────────────────────────────┐
│ Pin │ Connection │
├──────────────┼──────────────────────────────────────────────────────┤
│ VDD (24) │ VBUS_IN + C2 (100nF) to GND │
│ CC1 (2) │ USB-C CC1, also to CC1DB (pin 1) │
│ CC2 (4) │ USB-C CC2, also to CC2DB (pin 5) │
│ CC1DB (1) │ Tie to CC1 (enables dead battery mode) │
│ CC2DB (5) │ Tie to CC2 (enables dead battery mode) │
│ VBUS_EN_SNK (16) │ To gate drive (R12) → Q1 gate │
│ VREG_2V7 (23)│ C30 (1µF) to GND, also to VSYS (pin 22) │
│ VREG_1V2 (21)│ C34 (1µF) to GND │
│ VSYS (22) │ Tie to VREG_2V7 │
│ RESET (6) │ GND (or NC) - Active-HIGH, has internal pull-down │
│ DISCH (9) │ R13 (470Ω) to VBUS_OUT (for VBUS discharge) │
│ ADDR0 (12) │ GND │
│ ADDR1 (13) │ GND (I2C address = 0x28) │
│ GND (10) │ System GND │
│ EP (25) │ System GND (thermal pad) │
│ NC pins │ 3,7,8,11,14,15,17,18,19,20 - Not connected │
└──────────────┴──────────────────────────────────────────────────────┘
Connection List
Diagram2: USB-PD +15V → +13.5V Buck Converter (LM2596S-ADJ #1)
Key Points:
- Two-stage design: Buck converter (U2) reduces voltage with high efficiency, then linear regulator (LM7812) provides low-noise final output
- Capacitor order: C5/C6 (input filter) → [U2 + L1] → C3 (buck output filter) → [LM7812] → output capacitors
- C3 role: Filters switching ripple from buck converter before feeding the linear regulator
- Switching node: Junction at OUTPUT pin 2, where L1 and D1 cathode connect
- D1 flyback path: Provides current path when U2's internal switch is OFF (D1 cathode → switching node; D1 anode → GND)
- L1 output and D1 anode are completely separate paths - they do NOT connect to each other
View ASCII art circuit
Connection List
Diagram3: +15V → +7.5V Buck Converter (LM2596S-ADJ #2, U3)
Key Points:
- Switching node is the junction at OUTPUT pin 2
- Path 1: Switching node → L2 → +7.5V output (main current path)
- Path 2: Switching node → D2 cathode; D2 anode → GND (flyback/freewheeling path)
- D2 has exactly 2 connections: cathode to switching node, anode to GND
- L2 output and D2 anode are completely separate paths - they do NOT connect to each other
View ASCII art circuit
Connection List
Diagram4: +15V → -13.5V Inverting Buck-Boost (LM2596S-ADJ, U4)
Key Points:
- Inverting buck-boost topology: LM2596S-ADJ configured to convert positive input to negative output in a single stage
- Bootstrapped ground: IC GND pin connected to negative output (-13.5V), allowing FB pin to regulate correctly
- High efficiency: Single-stage conversion eliminates intermediate -15V stage
- Same IC family: Uses LM2596S-ADJ (same as Diagram2/3 buck converters)
- Input voltage: +15V from USB-PD
- Output voltage: -13.5V (feeds LM7912 linear regulator for final -12V output)
- Current capability: 800mA+ (sufficient for -12V rail)
- Switching frequency: 150kHz (LM2596 default)
View ASCII art circuit
Connection List
Diagram5: +13.5V → +12V Linear Regulator (L7812, U6)
Capacitor Placement (Critical for PCB layout):
- C26/C17 (ceramic): Place RIGHT NEXT to IC pins (minimize trace length for high-freq filtering)
- C20/C21 (electrolytic): Can be placed farther from IC (bulk storage, less sensitive to distance)
Key Points:
- Two-stage design: Buck converter (U2) provides efficient voltage reduction, linear regulator (U6) provides low-noise final output
- Input capacitor order: C20 (bulk, farther) and C26 (ceramic, close to IC)
- Output capacitor order: C17 (ceramic, close to IC) and C21 (bulk, farther)
- LED indicator: Green LED (LED2) with 1kΩ current-limiting resistor shows +12V rail is active
- Dropout voltage: LM7812 requires ~2V dropout, so 13.5V input provides 1.5V headroom
Protection Circuit (+12V Rail, 1.2A target, 1.5A max):
- Protection layers: LM7812 current limiting (~2.2A max) → LM7812 thermal shutdown (150°C) → PTC1 trips (>4A) → USB-PD adapter protection
- PTC1: C20808 (SMD1210P200TF) - 2.0A hold, 4A trip, auto-reset fuse with 67% margin above 1.2A operation
- TVS1: SMAJ15A (unidirectional, 15V) - Overvoltage protection (cathode to +12V OUT, anode to GND)
- Operation: Normal (<2.0A) = PTC low resistance, LED on; Overload (2.0A-4A) = PTC heats/trips in 1-5s; Short circuit (>4A) = LM7812 current limiting + PTC trips in 0.5-5s; Auto-reset after 30-60s cooling
View ASCII art circuit
Connection List
Diagram6: +7.5V → +5V Linear Regulator (L7805, U7)
Capacitor Placement (Critical for PCB layout):
- C27/C18 (ceramic): Place RIGHT NEXT to IC pins (minimize trace length for high-freq filtering)
- C22/C23 (electrolytic): Can be placed farther from IC (bulk storage, less sensitive to distance)
Key Points:
- Two-stage design: Buck converter (U3) provides efficient voltage reduction, linear regulator (U7) provides low-noise final output
- Input capacitor order: C22 (bulk, farther) and C27 (ceramic, close to IC)
- Output capacitor order: C18 (ceramic, close to IC) and C23 (bulk, farther)
- LED indicator: Blue LED (LED3) with 330Ω current-limiting resistor shows +5V rail is active
- LED current: I = (5V - 2.8V) / 330Ω = 6.67mA (improved brightness vs previous 1kΩ design)
- Dropout voltage: LM7805 requires ~2V dropout, so 7.5V input provides 2.5V headroom
Protection Circuit (+5V Rail, 0.5A target, 1A max):
- Protection layers: LM7805 current limiting (~1A max) → LM7805 thermal shutdown (150°C) → PTC2 trips (>2.2A) → USB-PD adapter protection
- PTC2: C70119 (mSMD110-33V) - 1.1A hold, 2.2A trip, auto-reset fuse
- TVS2: SD05 (unidirectional, 5V standoff) - Overvoltage protection optimized for DC power rail
- Operation: Normal (<1.1A) = PTC low resistance, LED on; Overload (1.1A-2.2A) = PTC heats/trips in 1-5s; Short circuit (>2.2A) = LM7805 current limiting + PTC trips in 1-5s; Auto-reset after 30-60s cooling
View ASCII art circuit
Connection List
Diagram7: -13.5V → -12V Linear Regulator (CJ7912, U8)
Capacitor Placement (Critical for PCB layout):
- C28/C19 (ceramic): Place RIGHT NEXT to IC pins (minimize trace length for high-freq filtering)
- C24/C25 (electrolytic): Can be placed farther from IC (bulk storage, less sensitive to distance)
Important: Negative Voltage Component Polarities
- Electrolytic capacitors REVERSED: C24 and C25 have negative terminal to negative voltage, positive terminal to GND
- LED polarity REVERSED: LED4 anode to GND (0V, highest potential), cathode through R16 to -12V (lowest potential)
Key Points:
- Two-stage design: Buck converter (U4) provides efficient voltage reduction, linear regulator (U8) provides low-noise final output
- Input capacitor order: C24 (bulk, farther) and C28 (ceramic, close to IC)
- Output capacitor order: C19 (ceramic, close to IC) and C25 (bulk, farther)
- LED indicator: Red LED (LED4) with 1kΩ current-limiting resistor shows -12V rail is active
- LED current: I = (0V - 2V - (-12V)) / 1kΩ = 10mA (current flows from GND through LED to -12V)
- Dropout voltage: LM7912 requires ~2V dropout, so -13.5V input provides 1.5V headroom
- LM7912 pinout: Different from positive regulators - pin 1=GND, pin 2=IN, pin 3=OUT (79xx series)
Protection Circuit (-12V Rail, 0.8A target, 1A max):
- Protection layers: LM7912 current limiting (~1A max) → LM7912 thermal shutdown (150°C) → PTC3 trips (>3.0A) → USB-PD adapter protection
- PTC3: C883133 (BSMD1206-150-16V) - 1.5A hold, 3.0A trip, auto-reset fuse with 88% margin above 0.8A operation
- TVS3: SMAJ15A (unidirectional, 15V) - Anode to -12V OUT, Cathode to GND (reversed for negative rail)
- Operation: Normal (<1.5A) = PTC low resistance, LED on; Overload (1.5A-3.0A) = PTC heats/trips in 1-5s; Short circuit (>3.0A) = LM7912 current limiting + PTC trips in 0.5-5s; Auto-reset after 30-60s cooling